As the critical dimensions of complementary metal oxide semiconductor (CMOS) devices continue to shrink, novel materials need to be incorporated into CMOS architecture, for example, to improve energy efficiency and/or speed. One such group of materials is III-V materials, which may be utilized, for example, in the channel of a transistor device. Unfortunately, current processing apparatus and methods fail to yield III-V films having suitable material quality, such as low defect density, composition control, high purity, morphology, in-wafer uniformity, and run to run reproducibility. Further, current processing apparatus for III-V materials are not integrated, for example in a cluster tool, with other CMOS device processing apparatus, for example such as process chambers to facilitate pre-clean, annealing, and/or deposition of high-k dielectric materials, due to compatibility issues. For example, such compatibility issues may be small substrate sizes, poor III-V film purity or quality, and/or poor chamber serviceability.
Accordingly, the inventors have provided improved methods and apparatus for the deposition of materials on a substrate, such as for example, III-V materials.